
//      
//      Copyright (c) 2002 Verisilicon  All Rights Reserved.
//     
//      Verilog model for Synchronous Two-Port Register File
//      Version:         2.6
//      Verified With:   Cadence Verilog-XL
//
//      Instance Name:   RFTP1024X11M4
//      Word Depth:      1024 
//      Word Width:      11 
//      Generation Date: 2011-4-26 0:38:22
//

`timescale 1 ns/10 ps
`celldefine

module RFTP1024X11M4 (DAOUT,ADA,ADB,CENA,CENB,CLKA,CLKB,DBIN);
 
  parameter     Word_Width=11;
  parameter     Word_Depth=1024;
  parameter	Addr_Depth=10;
   
  output [Word_Width-1:0] DAOUT;
  input                   CLKA;
  input                   CLKB;
  input                   CENA;
  input                   CENB;
  input  [Addr_Depth-1:0] ADA;
  input  [Addr_Depth-1:0] ADB;
  input  [Word_Width-1:0] DBIN;  
  wire   [Word_Width-1:0] DAOUT_int;
  wire   [Addr_Depth-1:0] ADA_int;
  wire   [Addr_Depth-1:0] ADB_int;
  wire                    CENA_int;
  wire                    CENB_int;
  wire                    CLKA_int;
  wire                    CLKB_int;
  wire   [Word_Width-1:0] DBIN_int;  
  reg    [Word_Width-1:0] DAOUT_state;
  reg    [Addr_Depth-1:0] ADA_state;
  reg    [Addr_Depth-1:0] ADB_state;
  reg                     CENA_state;
  reg                     CENB_state;
  reg                     CLKA_state;
  reg                     CLKB_state;  
  reg    [Word_Width-1:0] DBIN_state;
  reg                     flag_ADA0;
  reg                     flag_ADB0;
  reg                     flag_ADA1;
  reg                     flag_ADB1;
  reg                     flag_ADA2;
  reg                     flag_ADB2;
  reg                     flag_ADA3;
  reg                     flag_ADB3;
  reg                     flag_ADA4;
  reg                     flag_ADB4;
  reg                     flag_ADA5;
  reg                     flag_ADB5;
  reg                     flag_ADA6;
  reg                     flag_ADB6;
  reg                     flag_ADA7;
  reg                     flag_ADB7;
  reg                     flag_ADA8;
  reg                     flag_ADB8;
  reg                     flag_ADA9;
  reg                     flag_ADB9;
  reg                     flag_CENA;
  reg                     flag_CENB;
  reg                     flag_CLKA_CYC;
  reg                     flag_CLKA_HT;
  reg                     flag_CLKA_LT;
  reg                     flag_CLKB_CYC;
  reg                     flag_CLKB_HT;
  reg                     flag_CLKB_LT;  
  reg                     flag_DBIN0;
  reg                     flag_DBIN1;
  reg                     flag_DBIN2;
  reg                     flag_DBIN3;
  reg                     flag_DBIN4;
  reg                     flag_DBIN5;
  reg                     flag_DBIN6;
  reg                     flag_DBIN7;
  reg                     flag_DBIN8;
  reg                     flag_DBIN9;
  reg                     flag_DBIN10;
  reg                     flag_VIOA;
  reg                     flag_VIOB;
  reg                     prev_flag_ADA0;
  reg                     prev_flag_ADB0;
  reg                     prev_flag_ADA1;
  reg                     prev_flag_ADB1;
  reg                     prev_flag_ADA2;
  reg                     prev_flag_ADB2;
  reg                     prev_flag_ADA3;
  reg                     prev_flag_ADB3;
  reg                     prev_flag_ADA4;
  reg                     prev_flag_ADB4;
  reg                     prev_flag_ADA5;
  reg                     prev_flag_ADB5;
  reg                     prev_flag_ADA6;
  reg                     prev_flag_ADB6;
  reg                     prev_flag_ADA7;
  reg                     prev_flag_ADB7;
  reg                     prev_flag_ADA8;
  reg                     prev_flag_ADB8;
  reg                     prev_flag_ADA9;
  reg                     prev_flag_ADB9;
  reg                     prev_flag_CENA;
  reg                     prev_flag_CENB;
  reg                     prev_flag_CLKA_CYC;
  reg                     prev_flag_CLKA_HT;
  reg                     prev_flag_CLKA_LT;
  reg                     prev_flag_CLKB_CYC;
  reg                     prev_flag_CLKB_HT;
  reg                     prev_flag_CLKB_LT;  
  reg                     prev_flag_DBIN0;
  reg                     prev_flag_DBIN1;
  reg                     prev_flag_DBIN2;
  reg                     prev_flag_DBIN3;
  reg                     prev_flag_DBIN4;
  reg                     prev_flag_DBIN5;
  reg                     prev_flag_DBIN6;
  reg                     prev_flag_DBIN7;
  reg                     prev_flag_DBIN8;
  reg                     prev_flag_DBIN9;
  reg                     prev_flag_DBIN10;
  reg                     prev_flag_VIOA;
  reg                     prev_flag_VIOB;
  reg                     prev_CLKA;
  reg                     prev_CLKB;
  reg                     flag_A;
  reg                     flag_B;
  wire                    flag_opA;
  wire                    flag_opB;
  wire                    flag_confA;
  wire                    flag_confB;
  wire                    flag_conf;
  reg    [Word_Width-1:0] mem_array[Word_Depth-1:0];
  integer                 i;

  buf daout_buf[Word_Width-1:0] (DAOUT,DAOUT_int);
  buf ada_buf[Addr_Depth-1:0] (ADA_int,ADA);
  buf adb_buf[Addr_Depth-1:0] (ADB_int,ADB);
  buf (CENA_int,CENA);
  buf (CENB_int,CENB);
  buf (CLKA_int,CLKA);
  buf (CLKB_int,CLKB);
  buf dbin_buf[Word_Width-1:0] (DBIN_int,DBIN);
  
  assign DAOUT_int=DAOUT_state;
  assign flag_confA=(ADA_int===ADB_state)
                    && (CENA_int!==1'b1) && (CENB_state!==1'b1);
  assign flag_confB=(ADB_int===ADA_state)
                    && (CENB_int!==1'b1) && (CENA_state!==1'b1);		         
  assign flag_conf =(ADB_int===ADA_int)
                    && (CENB_int!==1'b1) && (CENA_int!==1'b1);
  assign flag_opA=!CENA_int;
  assign flag_opB=!CENB_int;

  always @(CLKA_int)
    begin
      CLKA_state=1'b0;
      if(CLKA_int===1'b1 && prev_CLKA===1'b0)
	begin
	  ADA_state=ADA_int;
	  CENA_state=CENA_int;
	  rw_memA;
	end
      else if(CLKA_int===1'bx) 
        begin
	  CLKA_state=1'bx;
	  rw_memA;
	end 
      prev_CLKA=CLKA_int;
    end
    
  always @(CLKB_int)
    begin
      CLKB_state=1'b0;
      if(CLKB_int===1'b1 && prev_CLKB===1'b0)
	begin
	  ADB_state=ADB_int;
	  DBIN_state=DBIN_int;
	  CENB_state=CENB_int;
	  rw_memB;
	end
      else if(CLKB_int===1'bx) 
        begin
	  CLKB_state=1'bx;
	  rw_memB;
	end 
      prev_CLKB=CLKB_int;
    end

  always @(flag_CENA
           or flag_ADA0
           or flag_ADA1
           or flag_ADA2
           or flag_ADA3
           or flag_ADA4
           or flag_ADA5
           or flag_ADA6
           or flag_ADA7
           or flag_ADA8
           or flag_ADA9
           or flag_CLKA_CYC or flag_CLKA_HT or flag_CLKA_LT
           or flag_VIOA)
    begin
      if(flag_ADA0!==prev_flag_ADA0) 
        ADA_state[0]=1'bx;
      prev_flag_ADA0=flag_ADA0;    
      if(flag_ADA1!==prev_flag_ADA1) 
        ADA_state[1]=1'bx;
      prev_flag_ADA1=flag_ADA1;    
      if(flag_ADA2!==prev_flag_ADA2) 
        ADA_state[2]=1'bx;
      prev_flag_ADA2=flag_ADA2;    
      if(flag_ADA3!==prev_flag_ADA3) 
        ADA_state[3]=1'bx;
      prev_flag_ADA3=flag_ADA3;    
      if(flag_ADA4!==prev_flag_ADA4) 
        ADA_state[4]=1'bx;
      prev_flag_ADA4=flag_ADA4;    
      if(flag_ADA5!==prev_flag_ADA5) 
        ADA_state[5]=1'bx;
      prev_flag_ADA5=flag_ADA5;    
      if(flag_ADA6!==prev_flag_ADA6) 
        ADA_state[6]=1'bx;
      prev_flag_ADA6=flag_ADA6;    
      if(flag_ADA7!==prev_flag_ADA7) 
        ADA_state[7]=1'bx;
      prev_flag_ADA7=flag_ADA7;    
      if(flag_ADA8!==prev_flag_ADA8) 
        ADA_state[8]=1'bx;
      prev_flag_ADA8=flag_ADA8;    
      if(flag_ADA9!==prev_flag_ADA9) 
        ADA_state[9]=1'bx;
      prev_flag_ADA9=flag_ADA9;    
      if(flag_CENA!==prev_flag_CENA) 
        CENA_state=1'bx;
      prev_flag_CENA=flag_CENA;
      if(!((flag_CLKA_CYC===prev_flag_CLKA_CYC) &&
    	 (flag_CLKA_HT===prev_flag_CLKA_HT) &&
    	 (flag_CLKA_LT===prev_flag_CLKA_LT)))
  	if(CENA_int!==1'b1) CLKA_state=1'bx;
      prev_flag_CLKA_CYC=flag_CLKA_CYC;
      prev_flag_CLKA_HT=flag_CLKA_HT;
      prev_flag_CLKA_LT=flag_CLKA_LT;
      if(flag_VIOA!==prev_flag_VIOA)
        begin
	  if(flag_B===1'b0)
	    DAOUT_state={Word_Width{1'bx}};
	  prev_flag_VIOA=flag_VIOA;
	end            
      else 
        rw_memA;
    end

  always @(flag_CENB
           or flag_ADB0
           or flag_ADB1
           or flag_ADB2
           or flag_ADB3
           or flag_ADB4
           or flag_ADB5
           or flag_ADB6
           or flag_ADB7
           or flag_ADB8
           or flag_ADB9
           or flag_CLKB_CYC or flag_CLKB_HT or flag_CLKB_LT
           or flag_DBIN0
           or flag_DBIN1
           or flag_DBIN2
           or flag_DBIN3
           or flag_DBIN4
           or flag_DBIN5
           or flag_DBIN6
           or flag_DBIN7
           or flag_DBIN8
           or flag_DBIN9
           or flag_DBIN10
           or flag_VIOB)
    begin
      if(flag_ADB0!==prev_flag_ADB0) 
        ADB_state[0]=1'bx;
      prev_flag_ADB0=flag_ADB0;    
      if(flag_ADB1!==prev_flag_ADB1) 
        ADB_state[1]=1'bx;
      prev_flag_ADB1=flag_ADB1;    
      if(flag_ADB2!==prev_flag_ADB2) 
        ADB_state[2]=1'bx;
      prev_flag_ADB2=flag_ADB2;    
      if(flag_ADB3!==prev_flag_ADB3) 
        ADB_state[3]=1'bx;
      prev_flag_ADB3=flag_ADB3;    
      if(flag_ADB4!==prev_flag_ADB4) 
        ADB_state[4]=1'bx;
      prev_flag_ADB4=flag_ADB4;    
      if(flag_ADB5!==prev_flag_ADB5) 
        ADB_state[5]=1'bx;
      prev_flag_ADB5=flag_ADB5;    
      if(flag_ADB6!==prev_flag_ADB6) 
        ADB_state[6]=1'bx;
      prev_flag_ADB6=flag_ADB6;    
      if(flag_ADB7!==prev_flag_ADB7) 
        ADB_state[7]=1'bx;
      prev_flag_ADB7=flag_ADB7;    
      if(flag_ADB8!==prev_flag_ADB8) 
        ADB_state[8]=1'bx;
      prev_flag_ADB8=flag_ADB8;    
      if(flag_ADB9!==prev_flag_ADB9) 
        ADB_state[9]=1'bx;
      prev_flag_ADB9=flag_ADB9;    
      if(flag_CENB!==prev_flag_CENB) 
        CENB_state=1'bx;
      prev_flag_CENB=flag_CENB;
      if(!(flag_CLKB_CYC===prev_flag_CLKB_CYC) &&
    	 (flag_CLKB_HT===prev_flag_CLKB_HT) &&
    	 (flag_CLKB_LT===prev_flag_CLKB_LT))
  	if(CENB_int!==1'b1) CLKB_state=1'bx;
      prev_flag_CLKB_CYC=flag_CLKB_CYC;
      prev_flag_CLKB_HT=flag_CLKB_HT;
      prev_flag_CLKB_LT=flag_CLKB_LT;
      if(flag_DBIN0!==prev_flag_DBIN0) 
        DBIN_state[0]=1'bx;
      prev_flag_DBIN0=flag_DBIN0;
      if(flag_DBIN1!==prev_flag_DBIN1) 
        DBIN_state[1]=1'bx;
      prev_flag_DBIN1=flag_DBIN1;
      if(flag_DBIN2!==prev_flag_DBIN2) 
        DBIN_state[2]=1'bx;
      prev_flag_DBIN2=flag_DBIN2;
      if(flag_DBIN3!==prev_flag_DBIN3) 
        DBIN_state[3]=1'bx;
      prev_flag_DBIN3=flag_DBIN3;
      if(flag_DBIN4!==prev_flag_DBIN4) 
        DBIN_state[4]=1'bx;
      prev_flag_DBIN4=flag_DBIN4;
      if(flag_DBIN5!==prev_flag_DBIN5) 
        DBIN_state[5]=1'bx;
      prev_flag_DBIN5=flag_DBIN5;
      if(flag_DBIN6!==prev_flag_DBIN6) 
        DBIN_state[6]=1'bx;
      prev_flag_DBIN6=flag_DBIN6;
      if(flag_DBIN7!==prev_flag_DBIN7) 
        DBIN_state[7]=1'bx;
      prev_flag_DBIN7=flag_DBIN7;
      if(flag_DBIN8!==prev_flag_DBIN8) 
        DBIN_state[8]=1'bx;
      prev_flag_DBIN8=flag_DBIN8;
      if(flag_DBIN9!==prev_flag_DBIN9) 
        DBIN_state[9]=1'bx;
      prev_flag_DBIN9=flag_DBIN9;
      if(flag_DBIN10!==prev_flag_DBIN10) 
        DBIN_state[10]=1'bx;
      prev_flag_DBIN10=flag_DBIN10;
      if(flag_VIOB!==prev_flag_VIOB)
        begin
	  if(flag_A===1'b1)
	    DAOUT_state={Word_Width{1'bx}};
	  prev_flag_VIOB=flag_VIOB;
	end            
      else 
        rw_memB;
    end

  task rw_memA;
    begin
      flag_A = 1'bx;
      if(CLKA_state===1'bx) 
    	  DAOUT_state={Word_Width{1'bx}};
      else if(CENA_state===1'b0)
        begin
            flag_A = 1;
   	      if(^(ADA_state)===1'bx)
   	        DAOUT_state={Word_Width{1'bx}};
   	      else
		DAOUT_state=mem_array[ADA_state];
        end
      else if(CENA_state===1'bx)
        begin
            flag_A = 1;
   	    DAOUT_state={Word_Width{1'bx}};
        end
    end
  endtask
  
    task rw_memB;
    begin
      flag_B = 1'bx;
      if(CLKB_state===1'bx) 
        begin
	  for(i=0;i<Word_Depth;i=i+1)
    	    mem_array[i]={Word_Width{1'bx}};
    	end
      else if(CENB_state===1'b0)
        begin
              flag_B = 0;
   	      if(^(ADB_state)===1'bx)
                begin
                  for (i=0;i<Word_Depth;i=i+1)
                  mem_array[i]={Word_Width{1'bx}};
                end
   	      else
                  mem_array[ADB_state]=DBIN_state;
        end
      else if(CENB_state===1'bx)
        begin
	    flag_B = 0;
   	    if(^(ADB_state)===1'bx)
              begin
                for(i=0;i<Word_Depth;i=i+1)
   	        mem_array[i]={Word_Width{1'bx}};   	        
              end
            else
		mem_array[ADB_state]={Word_Width{1'bx}};
        end
    end
  endtask  

  specify
    (posedge CLKA=>(DAOUT[0] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[1] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[2] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[3] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[4] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[5] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[6] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[7] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[8] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[9] : 1'bx))=(1.000,1.000);
    (posedge CLKA=>(DAOUT[10] : 1'bx))=(1.000,1.000);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[0],0,0,flag_ADA0);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[0],0,0,flag_ADA0);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[0],0,0,flag_ADB0);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[0],0,0,flag_ADB0);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[1],0,0,flag_ADA1);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[1],0,0,flag_ADA1);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[1],0,0,flag_ADB1);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[1],0,0,flag_ADB1);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[2],0,0,flag_ADA2);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[2],0,0,flag_ADA2);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[2],0,0,flag_ADB2);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[2],0,0,flag_ADB2);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[3],0,0,flag_ADA3);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[3],0,0,flag_ADA3);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[3],0,0,flag_ADB3);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[3],0,0,flag_ADB3);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[4],0,0,flag_ADA4);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[4],0,0,flag_ADA4);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[4],0,0,flag_ADB4);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[4],0,0,flag_ADB4);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[5],0,0,flag_ADA5);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[5],0,0,flag_ADA5);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[5],0,0,flag_ADB5);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[5],0,0,flag_ADB5);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[6],0,0,flag_ADA6);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[6],0,0,flag_ADA6);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[6],0,0,flag_ADB6);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[6],0,0,flag_ADB6);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[7],0,0,flag_ADA7);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[7],0,0,flag_ADA7);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[7],0,0,flag_ADB7);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[7],0,0,flag_ADB7);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[8],0,0,flag_ADA8);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[8],0,0,flag_ADA8);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[8],0,0,flag_ADB8);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[8],0,0,flag_ADB8);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[9],0,0,flag_ADA9);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[9],0,0,flag_ADA9);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[9],0,0,flag_ADB9);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[9],0,0,flag_ADB9);
    $setuphold(posedge CLKA,posedge CENA,0,0,flag_CENA);
    $setuphold(posedge CLKA,negedge CENA,0,0,flag_CENA);
    $setuphold(posedge CLKB,posedge CENB,0,0,flag_CENB);
    $setuphold(posedge CLKB,negedge CENB,0,0,flag_CENB);
    $period(posedge CLKA,2.000,flag_CLKA_CYC);
    $period(negedge CLKA,2.000,flag_CLKA_CYC);
    $period(posedge CLKB,2.000,flag_CLKB_CYC);
    $period(negedge CLKB,2.000,flag_CLKB_CYC);
    $width(posedge CLKA,1.000,0,flag_CLKA_HT);
    $width(posedge CLKB,1.000,0,flag_CLKB_HT);
    $width(negedge CLKA,1.000,0,flag_CLKA_LT);
    $width(negedge CLKB,1.000,0,flag_CLKB_LT);
    $setup(posedge CLKA,posedge CLKB &&& flag_confB,2.000,flag_VIOB);
    $setup(posedge CLKB,posedge CLKA &&& flag_confA,2.000,flag_VIOA);
    $hold(posedge CLKA,posedge CLKB &&& flag_conf,0.010,flag_VIOB);
    $hold(posedge CLKB,posedge CLKA &&& flag_conf,0.010,flag_VIOA);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[0],0,0,flag_DBIN0);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[0],0,0,flag_DBIN0);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[1],0,0,flag_DBIN1);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[1],0,0,flag_DBIN1);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[2],0,0,flag_DBIN2);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[2],0,0,flag_DBIN2);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[3],0,0,flag_DBIN3);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[3],0,0,flag_DBIN3);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[4],0,0,flag_DBIN4);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[4],0,0,flag_DBIN4);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[5],0,0,flag_DBIN5);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[5],0,0,flag_DBIN5);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[6],0,0,flag_DBIN6);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[6],0,0,flag_DBIN6);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[7],0,0,flag_DBIN7);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[7],0,0,flag_DBIN7);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[8],0,0,flag_DBIN8);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[8],0,0,flag_DBIN8);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[9],0,0,flag_DBIN9);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[9],0,0,flag_DBIN9);
    $setuphold(posedge CLKB &&& flag_opB,posedge DBIN[10],0,0,flag_DBIN10);
    $setuphold(posedge CLKB &&& flag_opB,negedge DBIN[10],0,0,flag_DBIN10);
  endspecify

endmodule

`endcelldefine
